Modern integrated circuits (ICs) are capable of supporting a variety of different input/output (I/O) standards. Examples of I/O standards can include, but are not limited to, different varieties of Gunning Transceiver Logic (GTL) signaling such as GTL, GTL_DCI, and GTLP_DCI, Low Voltage Differential Signaling LVDS25, LVCMOS25, and the like. Each of these I/O standards specifies a set of attributes such as whether a reference voltage VREF is necessary, the value of any required VREF, whether a voltage supply VCC is needed for input (VCCI) or output (VCCO), and/or the value of any required VCCI or VCCO. This listing of I/O standards and attributes is not intended to be exhaustive, but rather illustrative of the many varieties of I/O standards and corresponding attributes that exist for use with ICs.
Most modern programmable ICs organize I/O objects of a circuit design into a limited number of physical I/O banks (banks) on the programmable IC. A programmable IC, such as a field programmable gate array (FPGA), can include 8 banks, although this number is not definitive of every type of programmable IC as different programmable ICs include different numbers of banks. In any case, each bank can be associated with a plurality of different I/O objects. The I/O objects that are assigned to a given bank must be configured according to compatible I/O standards. As such, the placement of I/O objects into a given bank can be said to be constrained by the organization of that bank. In illustration, some I/O standards require a specific VCCI or VCCO. A bank typically has a single VCC supply. Accordingly, only I/O objects configured according to I/O standards that have compatible VCC requirements can be assigned to the same bank. Other attributes of I/O standards may further restrict the set of banks to which a given I/O object can be assigned.
The task of assigning I/O objects to banks is commonly referred to as the “Select I/O placement problem.” Past techniques for solving the Select I/O placement problem have relied upon heuristics to automate I/O placement. One heuristic-based approach utilizes a combination of simulated annealing, bipartite matching, and constructive bin-packing to find a solution. Heuristic-based techniques, however, do have disadvantages. In particular, heuristic-driven techniques are not guaranteed to determine a feasible I/O placement solution despite the existence of such a solution. Further, heuristic techniques are not capable of identifying an inherently infeasible circuit design.
Another proposed solution for the I/O placement problem relies upon an Integer Linear Programming (ILP) formulation of the problem. This solution seeks to overcome the uncertainties of heuristic approaches discussed above. While a feasible solution to the Select I/O placement problem may be found through the use of ILP, such a solution typically is not optimal in terms of wire length or other metrics that may be used to determine the quality of the solution. The most optimal solution in terms of selected quality metrics, however, typically is not a feasible solution. That is, an optimal solution will typically locate I/O objects with conflicting I/O standards within the same bank.